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21611hkim 20101217-s00007 no.a1916-1/25 http://onsemi.com semiconductor components industries, llc, 2013 july, 2013 LC450029PKB overview the LC450029PKB is 1/4 duty and 1/3 duty general-purpose microcontroller-controlled lcd drivers that can be used in applications such as frequency display in products with electronic tuning. in addition to being capable to drive up to 208 segments directly. the internal oscillation circuit helps to reduce the number of external resistors and capacitors required. the chip shape is slim for cog (c hip-on-glass) implementation. the operating temperature range is from -40 c to +105 c application ? car or general consumer electronic lcd display equipment. features ? selectable 1/4-duty or 1/3-duty drive by the serial control data when 1/4-duty: capable of driving up to 208 segments when 1/3-duty: capable of driving up to 159 segments ? 1/3-bias only ? serial data input supports ccb* format communication with the system controller. (for 5v operation only) ? the power-saving mode is selectable by the serial control data, and supports low power consumption. ? adjustable the frame frequency of the common and se gment output waveforms by the serial control data ? selectable the internal oscillator operating or extern al clock operating mode by the serial control data ? high generality, since display data is displayed directly without the intervention of a decoder circuit. ? the inh pad allows all lcd segments to be forced to the off state. ? with a built-in oscillator circuit (externa l resistors and capacitors are unnecessary.) ? the stability of the lcd bias voltage is high by a bu ilt-in lcd bias generator with voltage-follower buffers. ? shipping form: chip with au bumps in tray. ? allowable operating voltage (v dd , v dd i) : +4.5v to +6.0v ? allowable wide operating temperature ranges : -40 c to +105 c ordering number : ena1916 cmos ic 1/4 and 1/3-duty general-purpose lcd display driver ? ccb is on semiconductor? ?s original format. all addresses are managed by on semiconductor? for this format. ? ccb is a registered trademark of semiconductor components industries, llc.
LC450029PKB no.a1916-2/25 specifications absolute maximum ratings at ta = 25 c, v ss = 0v parameter symbol conditions ratings unit maximum supply voltage v dd max, v dd i max v dd =v dd i -0.3 to +6.5 v v in 1 ce, cl, di, inh -0.3 to +6.5 input voltage v in 2 osci -0.3 to v dd i+0.3 v output voltage v out s1 to s53, com1 to com4 -0.3 to v dd +0.3 v i out 1 s1 to s53 300 a output current i out 2 com1 to com4 3 ma operating temperature topr -40 to +105 c storage temperature tstg -55 to +125 c (note) power supply pads (v dd , v dd i) should connect all pads to the same power supply. (see sample applications circuits) allowable operating ranges at ta = -40 to +105 c, v ss = 0v ratings parameter symbol conditions min typ max unit supply voltage v dd , v dd i v dd =v dd i 4.5 6.0 v v ih 1 ce, cl, di, inh 0.8v dd 6.0 input high-level voltage v ih 2 osci: external clock operating mode 0.8v dd v dd i v v il 1 ce, cl, di, inh 0 0.2v dd i input low-level voltage v il 2 osci: external clock operating mode 0 0.2v dd i v external clock operating frequency f ck osci: external clock operating mode [figure 4] 10 300 600 khz external clock duty cycle d ck osci: external clock operating mode [figure 4] 30 50 70 % data setup time tds cl, di [figure 2][figure 3] 160 ns data hold time tdh cl, di [figure 2][figure 3] 160 ns ce wait time tcp ce, cl [figure 2][figure 3] 160 ns ce setup time tcs ce, cl [figure 2][figure 3] 160 ns ce hold time tch ce, cl [figure 2][figure 3] 160 ns high-level clock pulse width t h cl [figure 2][figure 3] 160 ns low-level clock pulse width t l cl [figure 2][figure 3] 160 ns rise time tr ce, cl, di [figure 2][figure 3] 160 ns fall time tf ce, cl, di [figure 2][figure 3] 160 ns inh switching time tc inh , ce [figure 5][figure 6] 10 s (note) power supply pads (v dd , v dd i) should connect all pads to the same power supply. (see sample applications circuits) stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LC450029PKB no.a1916-3/25 electrical characteristics for the allowable operating ranges ratings parameter symbol pin conditions min typ max unit v h 1 ce, cl, di, inh 0.1v dd i hysteresis v h 2 osci external clock operating mode 0.1v dd i v i ih 1 ce, cl, di, inh v i = 6.0v 5.0 input high-level current i ih 2 osci v i = v dd i, external clock operating mode 5.0 a i il 1 ce, cl, di, inh v i = 0v -5.0 input low-level current i il 2 osci v i = 0v, external clock operating mode -5.0 a v oh 1 s1 to s53 i o = -20 a v dd -0.9 output high-level voltage v oh 2 com1 to com4 i o = -100 a v dd -0.9 v v ol 1 s1 to s53 i o = 20 a 0.9 output low-level voltage v ol 2 com1 to com4 i o = 100 a 0.9 v v mid 1 s1 to s53 i o = 20 a 2/3v dd -0.9 2/3v dd +0.9 v mid 2 s1 to s53 i o = 20 a 1/3v dd -0.9 1/3v dd +0.9 v mid 3 com1 to com4 i o = 100 a 2/3v dd -0.9 2/3v dd +0.9 output middle-level voltage *1 v mid 4 com1 to com4 i o = 100 a 1/3v dd -0.9 1/3v dd +0.9 v oscillator frequency fosc internal oscillator circuit internal oscillator operating mode 210 300 390 khz i dd 1 v dd , v dd i < power-saving mode > v dd =v dd i=6.0v 40 100 i dd 2 v dd , v dd i < internal oscillator operating mode > v dd =v dd i=6.0v driver outputs are open. 200 400 current drain (total value of v dd and v dd i) i dd 3 v dd , v dd i < external clock operating mode > v dd =v dd i=6.0v f ck =300khz driver outputs are open. 170 340 a *1: excluding the amount of voltage drop of the lcd bias generator which generates v dd 1 and v dd 2. (see figure 1.) [figure 1] v ss to common drivers and segment drivers v dd 2 v dd 1 v dd lcd bias generator excluding the amount of voltage drop of the lcd bias generator
LC450029PKB no.a1916-4/25 (1) when cl is stopped at the low level [figure 2] (2) when cl is stopped at the high level [figure 3] (3) osci pad clock timing in external clock operating mode [figure 4] osci t ck l t ck h f ck = 1 t ck h+ t ck l [khz] d ck = t ck h t ck h+ t ck l 100[%] v il 2 50% v ih 2 tds v il 1 v il 1 v il 1 v ih 1 50% v ih 1 v ih 1 tch tcs tcp tdh tr tf t tds v il 1 v il 1 v il 1 v ih 1 v ih 1 50% v ih 1 tch tcs tcp tdh tr tf t
LC450029PKB no.a1916-5/25 block diagram cl ce di com4 s1 s2 s4 s5 com3 com2 com1 v ss v dd shift register common driver inh s53 control register s3 clock generator vlogic regulator v dd 1 v dd 2 lcd bias generator segment driver & latch v dd i osci - + - + ccb interface
LC450029PKB no.a1916-6/25 pad functions symbol pad no. function active i/o handling when unused com1 to com4 2 to 5 common driver outputs. the frame frequency is fo[hz]. com4 pad outputs the v ss level in 1/3-duty. - o open s1 to s53 6 to 58 segment outputs for displaying the display dat a transferred by serial data input. s51 pad outputs the v ss level in 1/4-duty. s52 pad and s53 pad output the v ss level at the control data dn=?0?. s53 pad outputs the v ss level at external clock operating mode. - o open inh 61 display off control input ? inh = low (v ss ) ...display forced off (v ss level output) s1 to s53 = low (v ss ) com1 to com4 = low (v ss ) the internal oscillator stops. stops inputting external clock. serial data transfer can be used. ? inh = high (v dd )...display on enables the internal oscillator circuit. (internal oscillator operating mode) enables external clock input. (external clock operating mode) while display on, lcd outputs force off (v ss level output) by the control data bu=?1?. while display on, lcd outputs off (off waveforms output) by the control data sc=?1?. l i gnd (v ss ) ce 62 h i di 63 - i cl 64 serial data transfer inputs. must be connected to the controller. ce: chip enable di: transfer data cl: synchronization clock i gnd (v ss ) vlogic 65 used to monitor pad for the power supply voltage of the logic circuit. - o open v dd i 66 to 71 power supply pad. a power voltage of 4. 5 to 6.0v must be applied to these pads. - - - osci 72 this pad can also be used as the external clock input pad when the external clock operating mode is selected by control data. this pad must be connected to gnd at internal oscillator operating mode. - i gnd (v ss ) v ss 73 to 90 ground pad. must be connected to ground. - - - v dd 2 91 used to monitor pad for the lcd drive bias voltage (1/3 v dd ). - o open v dd 1 92 used to monitor pad for the lcd drive bias voltage (2/3 v dd ). - o open v dd 93 to 105 power supply pad. a power voltage of 4.5 to 6.0v must be applied to these pads. - - - dummy 1, 59, 60, 106 dummy pad. must not be used. - open open (note) ? power supply pads (v dd , v dd i) should connect all pads to the same power supply. (see sample applications circuits) ? gnd pad (v ss ) should connect all pads to the gnd. ? when logic input pads (inh , ce, di, cl, osci) are not us ed, must be fixed to gnd (v ss ). ? must not use monitor pads (vlogic, v dd 1, v dd 2) in an external circuit. ? must not connect dummy pad (dummy) mutually. mo reover, never use it in an external circuit.
LC450029PKB no.a1916-7/25 serial data input 1. 1/4 duty (1) when cl is stopped at the low level note: dd is the direction data. fixed data 18 bits b1 b0 d2 d1 0 1 d50 0 0 di cl ce 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 d51 0 00 exf 0 sc oc dn dt 0 0 bu 0 0 fc0 fc1 fc2 d52 d47 d48 d49 b1 b0 0 1 d54 d53 0 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 d104 d103 0 000 01 00 0 0 0 0 0 0 0 00 0 d101 d102 d99 d100 0 b1 b0 0 1 d106 d105 0 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 d152 d151 0 000 00 01 0 0 0 0 0 0 0 00 0000 0 d203 b1 b0 0 1 d154 d153 0 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 d204 0 000 01 01 0 0 0 0 0 d208 d207 d206 d205 d202 d201 d200 d199 dd 2 bits control data 18 bits display data 52 bits ccb address 8 bits dd 2 bits display data 52 bits ccb address 8 bits fixed data 22 bits dd 2 bits display data 48 bits ccb address 8 bits fixed data 14 bits dd 2 bits display data 56 bits ccb address 8 bits
LC450029PKB no.a1916-8/25 (2) when cl is stopped at the high level note: dd is the direction data. ? ccb address .......... ?41h? ? d1 to d208 ............ display data ? exf ....................... ratio of dividing fr equency in external clock opera ting mode setting control data ? dt ......................... 1/4-duty drive or 1/3-duty drive switching control data ? dn ......................... the number of the maximum display segments setting control data ? fc0 to fc2 ............ common/segment output waveform frame frequency control data ? oc ......................... internal oscillator operating mode/external clock operating mode switching control data ? sc .......................... segment on/off (off wa veform output) control data ? bu ......................... normal mode/power-saving mode control data fc0 sc b1 b0 d2 d1 0 0 0 0 1 0 d48 d47 di cl ce b3 b2 a1 a0 a3 a2 1 0 0 d50 d49 d52 d51 0 00 0 0 exf 0 dt 0 dn bu 0 0 0 oc fc1 fc2 0 b1 b0 0 0 0 0 1 0 d100 d54 d53 b3 b2 a1 a0 a3 a2 1 0 0 0 000 01 0 d104 d103 d102 d101 00 0 0 0 0 0 00 00 d99 0 b1 b0 0 0 0 0 1 0 d152 d106 d105 d151 b3 b2 a1 a0 a3 a2 1 0 0 0 000 00 1 00 0 0 0 0 0 0 0 00 0 0 0 0 0 b1 b0 0 0 0 0 1 0 d204 d154 d153 d203 b3 b2 a1 a0 a3 a2 1 0 0 0 000 01 1 00 0 0 0 0 0 d208 d207 d206 d205 d202 d201 d200 d199 fixed data 18 bits dd 2 bits control data 18 bits display data 52 bits ccb address 8 bits dd 2 bits display data 52 bits ccb address 8 bits fixed data 22 bits dd 2 bits display data 48 bits ccb address 8 bits fixed data 14 bits dd 2 bits display data 56 bits ccb address 8 bits
LC450029PKB no.a1916-9/25 2. 1/3 duty (1) when cl is stopped at the low level note: dd is the direction data. b1 b0 d2 d1 0 1 d50 0 0 di cl ce 0 0 0 d53 1 0 0 b3 b2 a1 a0 a3 a2 d51 0 d54 0 exf 0 sc oc dn dt 0 0 bu 0 0 fc0 fc1 fc2 d52 d47 d48 d49 b1 b0 0 1 d56 d55 0 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 d106 d105 0 000 01 00 0 0 0 0 0 0 0 d107 0 d108 d103 d104 d101 d102 0 b1 b0 0 1 d110 d109 0 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 d156 d155 0 000 00 01 0 0 0 0 0 0 0 00 d157 d158 d159 0 fixed data 16 bits dd 2 bits control data 16 bits display data 54 bits ccb address 8 bits dd 2 bits display data 54 bits ccb address 8 bits fixed data 19 bits dd 2 bits display data 51 bits ccb address 8 bits
LC450029PKB no.a1916-10/25 (2) when cl is stopped at the high level note: dd is the direction data. ? ccb address .......... ?41h? ? d1 to d208 ............ display data ? exf ....................... ratio of dividing fr equency in external clock opera ting mode setting control data ? dt ......................... 1/4-duty drive or 1/3-duty drive switching control data ? dn ......................... the number of the maximum display segments setting control data ? fc0 to fc2 ............ common/segment output waveform frame frequency control data ? oc ......................... internal oscillator operating mode/external clock operating mode switching control data ? sc .......................... segment on/off (off wa veform output) control data ? bu ......................... normal mode/power-saving mode control data fc0 sc b1 b0 d2 d1 0 0 0 0 1 d53 d48 d47 di cl ce b3 b2 a1 a0 a3 a2 1 0 0 d50 d49 d52 d51 0 d54 00 0 exf 0 dt 0 dn bu 0 0 0 oc fc1 fc2 0 b1 b0 0 0 0 0 1 d107 d102 d56 d55 b3 b2 a1 a0 a3 a2 1 0 0 0 d108 00 01 0 d106 d105 d104 d103 0 0 0 0 0 0 0 00 00 d101 0 b1 b0 0 0 0 0 1 0 d156 d110 d109 d155 b3 b2 a1 a0 a3 a2 1 0 0 0 000 00 1 0 0 0 0 0 0 0 0 0 00 d157 d158 d159 0 fixed data 16 bits dd 2 bits control data 16 bits display data 54 bits ccb address 8 bits dd 2 bits display data 54 bits ccb address 8 bits fixed data 19 bits dd 2 bits display data 51 bits ccb address 8 bits
LC450029PKB no.a1916-11/25 serial data transfer example 1. 1/4 duty ? when 153 or more segments are used all 320 bits (include ccb address) of serial data must be sent. ? when fewer than 153 segments are used one of 80, 160 and 240 bits of serial data must be sent, depending on the number of segments to be used. however, the serial data shown below (the d1 to d52 display data, the control data and dd=?00?) must always be sent. 2. 1/3 duty ? when 109 or more segments are used all 240 bits (include ccb address) of serial data must be sent. ? when fewer than 109 segments are used either 80 or 160 bits of serial data must be sent, depending on the number of segments to be used. however, the serial data shown below (the d1 to d54 display data, the control data and dd=?00?) must always be sent. 72 bits 8 bits d2 d1 d47 1 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d48 d49 d50 d51 0000 0 fc0 exf 0 0 0 dt dn fc1 fc2 oc sc bu 0 0 0 d52 72 bits 8 bits d2 d1 d47 d105 1 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d48 d49 d50 d51 0000 0 fc0 exf 0 0 0 dt dn fc1 fc2 oc sc bu 0 0 1 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d53 1 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d106 d54 d99 d100 d101 d102 d151 d152 00000000000 0 0 0 0 0 000 0 1 00000000000 0 0 0 0 0 00 0 1 d52 d103 d104 d153 1 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d154 d199 d204 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0000 d208 d207 d206 d205 d203 d202 d201 d200 72 bits 8 bits d2 d1 d47 1 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d48 d49 d50 d51 d53 d54 00 0 fc0 exf 0 0 0 dt dn fc1 fc2 oc sc bu 0 0 0 d52 72 bits 8 bits d2 d1 d47 d109 1 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d48 d49 d50 d51 d53 d54 00 0 fc0 exf 0 0 0 dt dn fc1 fc2 oc sc bu 0 0 1 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d55 1 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d110 d56 d101 d102 d103 d104 d155 d156 d107 d108 000000000 0 0 0 0 0 000 0 1 00000000000 0 0 0 0 0 00 0 1 d52 d105 d106 d157 d158 d159 0
LC450029PKB no.a1916-12/25 control data functions (1) exf ? ratio of dividing frequency in external clock operating mode setting control data this control data sets the ratio of dividing frequency of the external clock which input into the osci pad, when the external clock operating mode (oc=?1?) is set. however, th is data is effective only when external clock operating mode (oc= ?1?) is set. the frame frequency is adjustable by setting exf, fc0 to fc2 and oc. exf ratio of dividing frequency in external clock operating mode 0 f ck / 8 1 f ck (2) dt ?1/4-duty drive or 1/3-duty drive switching control data this control data bit selects either 1/4-duty drive or 1/3-duty drive. dt drive scheme s51 pad?s state 0 1/4-duty drive low (v ss ) level output 1 1/3-duty drive s51 (segment output) (3) dn ?the number of the maximum display segments setting control data this control data bit sets the number of the maximum display segments. the number of the maximum di splay segments pad?s state dn 1/4 duty 1/3 duty s52 s53 0 up to 200 segments up to 153 segments ?l? (v ss ) ?l? (v ss ) 1 up to 208 segments up to 159 segments s52 (segment ou tput) s53 (segment output) (note) s53 pad outputs v ss level in external clock operating mode. (4) fc0 to fc2 ?common/segment output waveform frame frequency control data these control data bits set the frame frequency of the common and segment output waveforms. the frame frequency is adjustable by setting exf, fc0 to fc2 and oc. control data frame frequency fo[hz] fc0 fc1 fc2 internal oscillator operating mode (the control data oc=?0?, fosc=300[khz]typ) external clock operating mode (the control data oc=?1?, exf=?0?) case is f ck =300[khz]. external clock operating mode (the control data oc=?1?, exf=?1?) case is f ck =38[khz]. 0 0 0 fosc/6144 =48.8[hz]typ f ck /6144 =48.8[hz] f ck /768 =49.5[hz] 0 0 1 fosc/4608 =65.1[hz]typ f ck /4608 =65.1[hz] f ck /576 =66.0[hz] 0 1 0 fosc/3072 =97.7[hz]typ f ck /3072 =97.7[hz] f ck /384 =99.0[hz] 0 1 1 fosc/2304 =130.2[hz]typ f ck /2304 =130.2[hz] f ck /288 =131.9[hz] 1 0 0 fosc/1536 =195.3[hz]typ f ck /1536 =195.3[hz] f ck /192 =197.9[hz] 1 0 1 fosc/1152 =260.4[hz]typ f ck /1152 =260.4[hz] f ck /144 =263.9[hz] 1 1 0 fosc/768 =390.6[hz]typ f ck /768 =390.6[hz] f ck /96 =395.8[hz] 1 1 1 fosc/3072 =97.7[hz]typ f ck /3072 =97.7[hz] f ck /384 =99.0[hz] (5) oc ?internal oscillator operating mode/external clock operating mode switching control data this control data bit selects either the internal oscillator operating mode or external clock operating mode. oc fundamental clock operating mode s53 pad?s state 0 internal oscillator operating mode s53 (segment output) 1 external clock operating mode low (v ss ) level output (6) sc ? segment on/off (off waveform output) control data this control data bit controls the on/off (off waveform output) state of all the segments. sc display state 0 on 1 off of all the segments (off waveform output) (7) bu ? normal mode/power-saving mode control data this control data bit selects either normal mode or power-saving mode. bu mode 0 normal mode 1 power-saving mode all of the common and segment output pads output the v ss level. in this mode, the internal oscillator circuit stops oscillati on if the ic is in the internal oscillator operating mode (oc=0), and the ic stops receiving external clock signals if the ic is in the external clock operating mode (oc=1).
LC450029PKB no.a1916-13/25 display data and output pad correspondence (1/4 duty) output pad com1 com2 com3 com4 output pad com1 com2 com3 com4 s1 d1 d2 d3 d4 s28 d109 d110 d111 d112 s2 d5 d6 d7 d8 s29 d113 d114 d115 d116 s3 d9 d10 d11 d12 s30 d117 d118 d119 d120 s4 d13 d14 d15 d16 s31 d121 d122 d123 d124 s5 d17 d18 d19 d20 s32 d125 d126 d127 d128 s6 d21 d22 d23 d24 s33 d129 d130 d131 d132 s7 d25 d26 d27 d28 s34 d133 d134 d135 d136 s8 d29 d30 d31 d32 s35 d137 d138 d139 d140 s9 d33 d34 d35 d36 s36 d141 d142 d143 d144 s10 d37 d38 d39 d40 s37 d145 d146 d147 d148 s11 d41 d42 d43 d44 s38 d149 d150 d151 d152 s12 d45 d46 d47 d48 s39 d153 d154 d155 d156 s13 d49 d50 d51 d52 s40 d157 d158 d159 d160 s14 d53 d54 d55 d56 s41 d161 d162 d163 d164 s15 d57 d58 d59 d60 s42 d165 d166 d167 d168 s16 d61 d62 d63 d64 s43 d169 d170 d171 d172 s17 d65 d66 d67 d68 s44 d173 d174 d175 d176 s18 d69 d70 d71 d72 s45 d177 d178 d179 d180 s19 d73 d74 d75 d76 s46 d181 d182 d183 d184 s20 d77 d78 d79 d80 s47 d185 d186 d187 d188 s21 d81 d82 d83 d84 s48 d189 d190 d191 d192 s22 d85 d86 d87 d88 s49 d193 d194 d195 d196 s23 d89 d90 d91 d92 s50 d197 d198 d199 d200 s24 d93 d94 d95 d96 s51 - - - - s25 d97 d98 d99 d100 s52 d201 d202 d203 d204 s26 d101 d102 d103 d104 s53 d205 d206 d207 d208 s27 d105 d106 d107 d108 (note) in external clock operating mode, s53 pad outputs v ss level. when dn is ?0?, s52 pad and s53 pad output v ss level. when duty is 1/4, s51 pad outputs v ss level. for example, the table below lists the output states for the s21 output pad. display data d81 d82 d83 d84 output pad (s21) state 0 0 0 0 the lcd segments corresponding to com1, com2, com3, and com4 are off. 0 0 0 1 the lcd segment corresponding to com4 is on. 0 0 1 0 the lcd segment corresponding to com3 is on. 0 0 1 1 the lcd segments corresponding to com3 and com4 are on. 0 1 0 0 the lcd segment corresponding to com2 is on. 0 1 0 1 the lcd segments corresponding to com2 and com4 are on. 0 1 1 0 the lcd segments corresponding to com2 and com3 are on. 0 1 1 1 the lcd segments corresponding to com2, com3, and com4 are on. 1 0 0 0 the lcd segment corresponding to com1 is on. 1 0 0 1 the lcd segments corresponding to com1 and com4 are on. 1 0 1 0 the lcd segments corresponding to com1 and com3 are on. 1 0 1 1 the lcd segments corresponding to com1, com3, and com4 are on. 1 1 0 0 the lcd segments corresponding to com1 and com2 are on. 1 1 0 1 the lcd segments corresponding to com1, com2, and com4 are on. 1 1 1 0 the lcd segments corresponding to com1, com2, and com3 are on. 1 1 1 1 the lcd segments corresponding to com1, com2, com3, and com4 are on.
LC450029PKB no.a1916-14/25 display data and output pad correspondence (1/3 duty) output pad com1 com2 com3 output pad com1 com2 com3 s1 d1 d2 d3 s28 d82 d83 d84 s2 d4 d5 d6 s29 d85 d86 d87 s3 d7 d8 d9 s30 d88 d89 d90 s4 d10 d11 d12 s31 d91 d92 d93 s5 d13 d14 d15 s32 d94 d95 d96 s6 d16 d17 d18 s33 d97 d98 d99 s7 d19 d20 d21 s34 d100 d101 d102 s8 d22 d23 d24 s35 d103 d104 d105 s9 d25 d26 d27 s36 d106 d107 d108 s10 d28 d29 d30 s37 d109 d110 d111 s11 d31 d32 d33 s38 d112 d113 d114 s12 d34 d35 d36 s39 d115 d116 d117 s13 d37 d38 d39 s40 d118 d119 d120 s14 d40 d41 d42 s41 d121 d122 d123 s15 d43 d44 d45 s42 d124 d125 d126 s16 d46 d47 d48 s43 d127 d128 d129 s17 d49 d50 d51 s44 d130 d131 d132 s18 d52 d53 d54 s45 d133 d134 d135 s19 d55 d56 d57 s46 d136 d137 d138 s20 d58 d59 d60 s47 d139 d140 d141 s21 d61 d62 d63 s48 d142 d143 d144 s22 d64 d65 d66 s49 d145 d146 d147 s23 d67 d68 d69 s50 d148 d149 d150 s24 d70 d71 d72 s51 d151 d152 d153 s25 d73 d74 d75 s52 d154 d155 d156 s26 d76 d77 d78 s53 d157 d158 d159 s27 d79 d80 d81 (note) in external clock operating mode, s53 pad outputs v ss level. when dn is ?0?, s52 pad and s53 pad output v ss level. for example, the table below lists the output states for the s21 output pad. display data d61 d62 d63 output pad (s21) state 0 0 0 the lcd segments corresponding to com1, com2, and com3 are off. 0 0 1 the lcd segment corresponding to com3 is on. 0 1 0 the lcd segment corresponding to com2 is on. 0 1 1 the lcd segments corresponding to com2 and com3 are on. 1 0 0 the lcd segment corresponding to com1 is on. 1 0 1 the lcd segments corresponding to com1 and com3 are on. 1 1 0 the lcd segments corresponding to com1 and com2 are on. 1 1 1 the lcd segments corresponding to com1, com2, and com3 are on.
LC450029PKB no.a1916-15/25 output waveforms (1/4-dut y 1/3-bias drive scheme) (note) the frame frequency fo[hz] is adjustable by setting control data (exf, fc0 to fc2 and oc). (see ?control data functions? for details) com3 com2 com1 com4 lcd driver output when all lcd segments corresponding to com1, com2, com3, and com4 are on. lcd driver output when lcd segments corresponding to com2 and com4 are on. lcd driver output when only lcd segments corresponding to com4 are on. lcd driver output when lcd segments corresponding to com1, com2, and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when all lcd segments corresponding to com1, com2, com3, and com4 are off. v dd 1 v dd 2 frame frequency fo[hz] v dd v ss v dd 1 v dd 2 v dd v ss v dd 1 v dd 2 v dd v ss v dd 1 v dd 2 v dd v ss v dd 1 v dd 2 v dd v ss v dd 1 v dd 2 v dd v ss v dd 1 v dd 2 v dd v ss v dd 1 v dd 2 v dd v ss v dd 1 v dd 2 v dd v ss v dd 1 v dd 2 v dd v ss v dd 1 v dd 2 v dd v ss v dd 1 v dd 2 v dd v ss v dd 1 v dd 2 v dd v ss v dd 1 v dd 2 v dd v ss v dd 1 v dd 2 v dd v ss
LC450029PKB no.a1916-16/25 output waveforms (1/3-duty 1/3-bias drive scheme) (note) the frame frequency fo[hz] is adjustable by setting control data (exf, fc0 to fc2 and oc). (see ?control data functions? for details) v dd 2 v dd 1 v dd v ss v dd 2 v dd 1 v dd v ss v dd 2 v dd 1 v dd v ss v dd 2 v dd 1 v dd v ss v dd 2 v dd 1 v dd v ss v dd 2 v dd 1 v dd v ss v dd 2 v dd 1 v dd v ss v dd 2 v dd 1 v dd v ss v dd 2 v dd 1 v dd v ss v dd 2 v dd 1 v dd v ss v dd 2 v dd 1 v ss frame frequency fo[hz] v dd com3 com2 com1 lcd driver output when all lcd segments corresponding to com1, com2, and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when all lcd segments corresponding to com1, com2, and com3 are off.
LC450029PKB no.a1916-17/25 display control and the inh pad since the lsi internal data (1/4 duty : the display data d1 to d208 and the control data, 1/3 duty : the display data d1 to d159 and the control data) is undefined when power is first applied. applications should set the inh pad low at the same time as power is applied to turn off the display (t his sets the s1 to s53 and com1 to com4 pads the v ss level.) and during this period send serial data from the controller. the controller should then set the inh pad high after the data transfer has completed. this procedure pr events meaningless display at power on. v dd and v dd i are connected with the same power supply. the timing of turn on and turn off for v dd and v dd i should be same time. (see from figure 5 to figure 8) ? 1/4 duty (note) the wait time (t1) which power supply turn on should be 1ms or more. the discharge time (t2) of lcd panel?s electric charge should be decided the optimum value according to the characteristic of the lcd panel. the switching time (tc) of inh should be 10 s or more. [figure 5] ? 1/3 duty (note) the wait time (t1) which power supply turn on should be 1ms or more. the discharge time (t2) of lcd panel?s electric charge should be decided the optimum value according to the characteristic of the lcd panel. the switching time (tc) of inh should be 10 s or more. [figure 6] initialization of display data and control data t2 ce inh v il 1 tc v il 1 t1 v dd =v dd i off (v ss level output) on update display data off (v ss level output) s1 to s53 com1 to com4 initialization of display data and control data t2 ce inh v il 1 tc v il 1 t1 v dd =v dd i off (v ss level output) on update display data off (v ss level output) s1 to s53 com1 to com4
LC450029PKB no.a1916-18/25 ? in external clock operating mode (note) the wait time (t1) which power supply turn on should be 1ms or more. the discharge time (t2) of lcd panel?s electric charge should be decided the optimum value according to the characteristic of the lcd panel. the switching time (tc) of inh should be 10 s or more. osci pad should be input an external clock at inh is high level. [figure 7] ? all segments off (off waveforms output) [figure 8] ? power-saving mode [figure 9] ce t1 v dd =v dd i osci t2 v il 1 tc v il 1 initialization of display data and control data (oc=1) update display data off (v ss level output) on off (v ss level output) s1 to s53 com1 to com4 inh ce v dd =v dd i s1 v ss v ss sc=1 sc=0 v ss com1 v ss off (off waveforms output) initialization of display data and control data (sc=0) off (v ss level output) on on off (v ss level output) inh ce v dd =v dd i s1 to s53 com1 to com4 bu=1 bu=0 initialization of display data and control data (bu=0) off (v ss level output) off (v ss level output) off (v ss level output) on on power-saving mode inh
LC450029PKB no.a1916-19/25 notes on controller transf er of display data when using the LC450029PKB in 1/4 duty, applications transfer the display data (d1 to d208) in four operations, and in 1/3 duty, they transfer the display data (d1 to d159) in three operations. in either case, applications should transfer all of the display data within 30ms to maintain the quality of displayed image. about peripheral circuit of the input pad (1) processing of unused osci pad when osci pad is not to be used, select the internal osc illator operating mode (control data oc=?0?), and osci pad is connected to gnd. osci
LC450029PKB no.a1916-20/25 sample applications circuit1 1/4 duty, display data (d1 to d208), internal oscillator operating mode sample applications circuit2 1/4 duty, display data (d1 to d204), external clock operating mode * 2 connect capacitors between a power supply line and gnd for noise removal and power supply stabilization. determine the value of a capacitor, after an actual circuit board estimates. * 3 in 1/4 duty, s51 pad outputs v ss level. * 4 when osci pad is not to be used, select the intern al oscillator operating mode (control data oc=?0?), and osci pad is connected to gnd. * 5 in external clock operating mode, s53 pad outputs v ss level. di cl ce osci com4 s5 s4 s2 s1 com3 com2 com1 *2 +5v s3 s50 s51 s52 s53 (open) *3 c vlogic (open) (open) (open) c v dd i controller *2 *4 v ss v dd 2 v dd 1 v dd inh lcd panel di cl ce osci com4 s5 s4 s2 s1 com3 com2 com1 +5v s3 s50 s51 s52 s53 (open) *3 vlogic (open) (open) (open) v dd i controller (open) *5 *2 c c *2 v ss v dd 2 v dd 1 v dd inh lcd panel
LC450029PKB no.a1916-21/25 sample applications circuit3 1/3 duty, display data (d1 to d159), internal oscillator operating mode * 2 connect capacitors between a power supply line and gnd for noise removal and power supply stabilization. determine the value of a capacitor, after an actual circuit board estimates. * 6 in 1/3 duty, com4 pad outputs v ss level. di cl ce osci com4 s5 s4 s2 s1 com3 com2 com1 +5v s3 s50 s51 s52 s53 (open) (open) (open) (open) *6 controller *2 c c *2 vlogic v dd i v ss v dd 2 v dd 1 v dd inh lcd panel
LC450029PKB no.a1916-22/25 the notes on use important things for stability operation of ic are shown as follows. the contents indicated below do not guarantee ic operation and the characteristic. moreover, the example of an application circuit written in these specifications is for explaining internal operation and usage. therefore, please perform the design in consideration of the specification of operation and terms and conditions in the actual lcd panel. (1) the design of power supply all power supply pads are connected to the power supply, and do not set open. (2) ito (indium tin oxide) wiring by designing the wire of power supply (v dd , v dd i, v ss ) wide and short, make the parasitic resistance of ito wiring into the minimum. (3) signal wiring and connection the dummy pad does not connect to anywhere, and sets open. (4) processing of unused input pad for cmos process, if an input pad is in open state, op eration of ic may become unstable, or unnecessary power supply current may flow through it. please be sure to connect the empty pad of a logic input to v ss . (5) the measure against shading the optical irradiation to ic causes the mis-operation of ic . when ic is implemented, take the measures against shading about the surface, back and side of ic.
LC450029PKB no.a1916-23/25 ? pad locations (bump side view) ? chip dimensions (x, y, s are based on the dicing center.) x=1.00mm y=4.08mm s=4.08mm 2 wafer thickness=400 m (typ) ? au bump dimensions (typ) size item pad no. x [ m] y [ m] s [ m 2 ] 1 to 59 108 27 2916 bump size 60 to 106 68 42 2856 10 to 58 50 - min. bump pitch 1 to 9, 59 to 106 - - 10 to 58, 66 to 71, 73 to 90, 93 to 105 23 - min. bump clearance 1 to 9, 59 to 65, 72, 91 to 92, 106 - - bump height all pads 17 - ? alignment marks (1) a-type (2) b-type (3) c-type x y (0, 0) alignment mark #1 (a-type) alignment mark #2 (b-type) alignment mark #3 (c-type) model name inh ce di cl vlogic pad no.66 v dd i pad no.71 v dd i pad no.72 osci pad no.73 v ss pad no.90 v ss pad no.91 v dd 2 pad no.92 v dd 1 pad no.93 v dd pad no.105 v dd pad no.60 dummy pad no.106 dummy dummy pad no.59 s53 pad no.58 s52 s51 s7 s6 s5 pad no.10 s4 s3 s2 s1 com4 com3 com2 com1 dummy pad no.1 10 30 60 10 30 60 80 50 50 80 80 50 50 80 20 20 unit:
LC450029PKB no.a1916-24/25 ? center coordinates of pads (all x/y coordinates represent the position of the center of each pad) pad no. pad name x [ m] y [ m] pad no. pad name x [ m] y [ m] pad no. pad name x [ m] y [ m] 1 dummy -380 1950 41 s36 -380 -943 81 v ss 400 10 2 com1 -380 1369 42 s37 -380 -993 82 v ss 400 75 3 com2 -380 1276 43 s38 -380 -1043 83 v ss 400 140 4 com3 -380 1183 44 s39 -380 -1093 84 v ss 400 205 5 com4 -380 1090 45 s40 -380 -1143 85 v ss 400 270 6 s1 -380 932 46 s41 -380 -1193 86 v ss 400 335 7 s2 -380 856 47 s42 -380 -1243 87 v ss 400 400 8 s3 -380 780 48 s43 -380 -1293 88 v ss 400 465 9 s4 -380 704 49 s44 -380 -1343 89 v ss 400 530 10 s5 -380 607 50 s45 -380 -1393 90 v ss 400 595 11 s6 -380 557 51 s46 -380 -1443 91 v dd 2 400 668 12 s7 -380 507 52 s47 -380 -1493 92 v dd 1 400 739 13 s8 -380 457 53 s48 -380 -1543 93 v dd 400 811 14 s9 -380 407 54 s49 -380 -1593 94 v dd 400 876 15 s10 -380 357 55 s50 -380 -1643 95 v dd 400 941 16 s11 -380 307 56 s51 -380 -1693 96 v dd 400 1006 17 s12 -380 257 57 s52 -380 -1743 97 v dd 400 1071 18 s13 -380 207 58 s53 -380 -1793 98 v dd 400 1136 19 s14 -380 157 59 dummy -380 -1950 99 v dd 400 1201 20 s15 -380 107 60 dummy 400 -1943 100 v dd 400 1266 21 s16 -380 57 61 inh 400 -1665 101 v dd 400 1331 22 s17 -380 7 62 ce 400 -1525 102 v dd 400 1396 23 s18 -380 -43 63 di 400 -1385 103 v dd 400 1461 24 s19 -380 -93 64 cl 400 -1245 104 v dd 400 1526 25 s20 -380 -143 65 vlogic 400 -1161 105 v dd 400 1591 26 s21 -380 -193 66 v dd i 400 -1071 106 dummy 400 1943 27 s22 -380 -243 67 v dd i 400 -1006 28 s23 -380 -293 68 v dd i 400 -941 29 s24 -380 -343 69 v dd i 400 -876 30 s25 -380 -393 70 v dd i 400 -811 31 s26 -380 -443 71 v dd i 400 -746 32 s27 -380 -493 72 osci 400 -650 33 s28 -380 -543 73 v ss 400 -510 34 s29 -380 -593 74 v ss 400 -445 35 s30 -380 -643 75 v ss 400 -380 36 s31 -380 -693 76 v ss 400 -315 37 s32 -380 -743 77 v ss 400 -250 38 s33 -380 -793 78 v ss 400 -185 39 s34 -380 -843 79 v ss 400 -120 40 s35 -380 -893 80 v ss 400 -55 ? center coordinates of alignment marks (all x/y coordinates represent the position of the center of each alignment mark) alignment mark type x [ m] y [ m] 1 a 400 -1800 2 b 400 1790 3 c -380 1800
LC450029PKB no.a1916-25/25 ps on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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